243 lines
15 KiB
C
243 lines
15 KiB
C
/*-*- mode:c;indent-tabs-mode:nil;c-basic-offset:2;tab-width:8;coding:utf-8 -*-│
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│vi: set net ft=c ts=8 sts=2 sw=2 fenc=utf-8 :vi│
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╞══════════════════════════════════════════════════════════════════════════════╡
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│ Copyright 2020 Justine Alexandra Roberts Tunney │
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│ │
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│ Permission to use, copy, modify, and/or distribute this software for │
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│ any purpose with or without fee is hereby granted, provided that the │
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│ above copyright notice and this permission notice appear in all copies. │
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│ │
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│ THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL │
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│ WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED │
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│ WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE │
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│ AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL │
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│ DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR │
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│ PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER │
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│ TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR │
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│ PERFORMANCE OF THIS SOFTWARE. │
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╠──────────────────────────────────────────────────────────────────────────────╣
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│░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░│
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│░░░░░░░█▀█░█░▄░░█░░█░█░█▀█░█░░░█░░░▀█▀░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░│
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│░░░░░░░▀░▀░▀▀▀░░▀░░▀▀▀░▀░▀░▀▀▀░▀▀▀░░▀░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░│
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│░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░│
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│░░░░░░░█▀█░█▀█░█▀█░▀█▀░█▀█░█▀█░█░░░█▀▀░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░│
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│░░░░░░░█▀▀░█ █░██▀░░█░░█▀█░█▀█░█░░░█▀▀░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░│
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│░░░░░░░▀░░░▀▀▀░▀░▀░░▀░░▀░▀░▀▀▀░▀▀▀░▀▀▀░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░│
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│░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░│
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│░░░░░░░█▀▀░█░█░█▀▀░█▀█░█░█░▀█▀░█▀█░█▀█░█░░█▀▀░░░░░░░░░░░░░░░░░░░░░░░░▄▄░░░▐█░░│
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│░░░░░░░█▀▀░▄▀▄░█▀▀░█░▄░█░█░░█░░█▀█░█▀█░█░░█▀▀░░░░░░░░░░░░▄▄▄░░░▄██▄░░█▀░░░█░▄░│
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│░░░░░░░▀▀▀░▀░▀░▀▀▀░▀▀▀░▀▀▀░░▀░░▀░▀░▀▀▀░▀▀░▀▀▀░░░░░░░░░░▄██▀█▌░██▄▄░░▐█▀▄░▐█▀░░│
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│░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░▐█▀▀▌░░░▄▀▌░▌░█░▌░░▌░▌░░│
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╠──────────────────────────────────────────────────────▌▀▄─▐──▀▄─▐▄─▐▄▐▄─▐▄─▐▄─│
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│ αcτµαlly pδrταblε εxεcµταblε § ibm personal computer │
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╚─────────────────────────────────────────────────────────────────────────────*/
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#ifndef APE_LIB_PC_H_
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#define APE_LIB_PC_H_
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#define BOOTSIG 0xaa55 /* master boot record signature */
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#define PC_BIOS_DATA_AREA 0x400
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#define kInterruptFlag (1u << 9)
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/* FPU Status Word (x87)
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@see Intel Manual V1 §8.1.3
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IE: Invalid Operation ────────────────┐
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DE: Denormalized Operand ────────────┐│
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ZE: Zero Divide ────────────────────┐││
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OE: Overflow Flag ─────────────────┐│││
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UE: Underflow Flag ───────────────┐││││
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PE: Precision Flag ──────────────┐│││││
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SF: Stack Fault ────────────────┐││││││
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ES: Exception Summary Status ──┐│││││││
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C0-3: Condition Codes ──┬────┐ ││││││││
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TOP of Stack Pointer ─────┐ │ ││││││││
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B: FPU Busy ───────────┐│ │ │ ││││││││
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││┌┴┐┌┼┐││││││││
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│↓│ │↓↓↓││││││││*/
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#define FPU_IE 0b0000000000100000000000001
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#define FPU_ZE 0b0000000000100000000000100
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#define FPU_SF 0b0000000000000000001000000
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#define FPU_C0 0b0000000000000000100000000
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#define FPU_C1 0b0000000000000001000000000
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#define FPU_C2 0b0000000000000010000000000
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#define FPU_C3 0b0000000000100000000000000
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#define CR0_PE (1u << 0) /* protected mode enabled */
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#define CR0_MP (1u << 1) /* monitor coprocessor */
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#define CR0_EM (1u << 2) /* no x87 fpu present if set */
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#define CR0_TS (1u << 3) /* task switched x87 */
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#define CR0_ET (1u << 4) /* extension type 287 or 387 */
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#define CR0_NE (1u << 5) /* enable x87 error reporting */
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#define CR0_WP (1u << 16) /* write protect read-only pages @pl0 */
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#define CR0_AM (1u << 18) /* alignment mask */
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#define CR0_NW (1u << 29) /* global write-through cache disable */
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#define CR0_CD (1u << 30) /* global cache disable */
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#define CR0_PG (1u << 31) /* paging enabled */
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#define CR4_VME (1u << 0) /* virtual 8086 mode extension */
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#define CR4_PVI (1u << 1) /* protected mode virtual interrupts */
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#define CR4_TSD (1u << 2) /* time stamp disable (rdtsc) */
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#define CR4_DE (1u << 3) /* debugging extensions */
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#define CR4_PSE (1u << 4) /* page size extension */
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#define CR4_PAE (1u << 5) /* physical address extension */
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#define CR4_MCE (1u << 6) /* machine check exception */
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#define CR4_PGE (1u << 7) /* page global enabled */
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#define CR4_OSFXSR (1u << 9) /* enable SSE and fxsave/fxrestor */
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#define CR4_OSXMMEXCPT (1u << 10) /* enable unmasked SSE exceptions */
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#define CR4_LA57 (1u << 12) /* enable level-5 paging */
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#define CR4_VMXE (1u << 13) /* enable VMX operations */
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#define CR4_SMXE (1u << 14) /* enable SMX operations */
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#define CR4_FSGSBASE (1u << 16) /* enable *FSBASE and *GSBASE instructions */
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#define CR4_PCIDE (1u << 17) /* enable process-context identifiers */
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#define CR4_OSXSAVE (1u << 18) /* enable XSAVE */
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#define XCR0_X87 (1u << 0)
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#define XCR0_SSE (1u << 1)
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#define XCR0_AVX (1u << 2)
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#define XCR0_BNDREG (1u << 3)
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#define XCR0_BNDCSR (1u << 4)
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#define XCR0_OPMASK (1u << 5)
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#define XCR0_ZMM_HI256 (1u << 6)
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#define XCR0_HI16_ZMM (1u << 7)
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#define EFER 0xC0000080 /* extended feature enable register */
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#define EFER_SCE (1u << 0) /* system call extensions */
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#define EFER_LME (1u << 8) /* long mode enable */
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#define EFER_LMA (1u << 10) /* long mode active */
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#define EFER_NXE (1u << 11) /* no-execute enable */
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#define GDT_REAL_CODE 8
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#define GDT_REAL_DATA 16
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#define GDT_LEGACY_CODE 24
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#define GDT_LEGACY_DATA 32
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#define GDT_LONG_CODE 40
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#define GDT_LONG_DATA 48
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#define PIC1 0x20 /* IO base address for master PIC */
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#define PIC2 0xA0 /* IO base address for slave PIC */
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#define PIC1_CMD PIC1
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#define PIC1_DATA (PIC1 + 1)
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#define PIC2_CMD PIC2
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#define PIC2_DATA (PIC2 + 1)
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#define PIC_EOI 0x20 /* End-of-interrupt command code */
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#define PIC_READ_IRR 0x0a /* OCW3 irq ready next CMD read */
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#define PIC_READ_ISR 0x0b /* OCW3 irq service next CMD read */
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/* Long Mode Paging
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@see Intel Manual V.3A §4.1 §4.5
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IsValid (ignored on CR3) V┐
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┌XD:No Inst. Fetches (if NXE) IsWritable (ignored on CR3) RW┐│
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│ Permit User-Mode Access - u┐││
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│ Page-level Write-Through - PWT┐│││
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│ Page-level Cache Disable - PCD┐││││
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│ Set if has been read - Accessed┐│││││
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│ Set if has been written - Dirty┐││││││
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│ IsPage (if PDPTE/PDE) or PAT (if PT)┐│││││││
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│ (If this maps 2MB/1GB page and CR4.PGE) Global┐││││││││
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│ (If IsPage 2MB/1GB, see Intel V3A § 11.12) PAT │││││││││
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│ │ │││││││││
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│ ┌────────────────────────────────────┤ │││││││││
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│ Must Be 0┐│ Next Page Table Address (!IsPage) │ │││││││││
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│ │├────────────────────────────────────┤ │││││││││
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│ ││ Physical Address 4KB │ │││││││││
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│┌───┐┌─────┐│├───────────────────────────┐ │ign│││││││││
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││PKE││ ign │││ Physical Address 2MB │ │┌┴┐│││││││││
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││ ││ ││├──────────────────┐ │ ││ ││││││││││
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││ ││ │││ Phys. Addr. 1GB │ │ ││ ││││││││││
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││ ││ │││ │ │ ││ ││││││││││
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6666555555555544444444443333333333222222222211111111110000000000
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3210987654321098765432109876543210987654321098765432109876543210*/
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#define PAGE_V /* */ 0b000000001
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#define PAGE_RW /* */ 0b000000010
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#define PAGE_U /* */ 0b000000100
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#define PAGE_4KB /* */ 0b010000000
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#define PAGE_2MB /* */ 0b110000000
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#define PAGE_1GB /* */ 0b110000000
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#define PAGE_TA 0b11111111111111111111111111111111111111000000000000
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#define PAGE_PA2 0b11111111111111111111111111111000000000000000000000
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#define PAGE_XD 0x8000000000000000
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#if !(__ASSEMBLER__ + __LINKER__ + 0)
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#include "ape/config.h"
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struct thatispacked GlobalDescriptorTable {
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uint16_t size;
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uint64_t *entries;
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};
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/**
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* Memory hole map.
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* @see wiki.osdev.org/Detecting_Memory_(x86)
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* @since 2002
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*/
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struct SmapEntry {
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uint64_t addr;
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uint64_t size;
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enum {
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kMemoryUsable = 1,
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kMemoryUnusable = 2,
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kMemoryAcpiReclaimable = 3,
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kMemoryAcpiNvs = 4,
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kMemoryBad = 5
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} type;
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uint32_t __acpi3; /* is abstracted */
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};
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struct IdtDescriptor {
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uint16_t offset_1; /* offset bits 0..15 */
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uint16_t selector; /* a code segment selector in GDT or LDT */
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uint8_t ist; /* bits 0..2 hold stack table offset, rest are zero */
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uint8_t type_attr; /* type and attributes */
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uint16_t offset_2; /* offset bits 16..31 */
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uint32_t offset_3; /* offset bits 32..63 */
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uint32_t zero; /* reserved */
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};
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struct thatispacked PageTable {
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uint64_t p[512];
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} forcealign(PAGESIZE);
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extern struct PageTable g_pml4t;
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extern struct GlobalDescriptorTable gdt;
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extern const unsigned char kBiosDataArea[256];
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extern const unsigned char kBiosDataAreaXlm[256];
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extern struct SmapEntry e820map[XLM_E820_SIZE / sizeof(struct SmapEntry)];
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extern struct SmapEntry e820map_xlm[XLM_E820_SIZE / sizeof(struct SmapEntry)];
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extern uint64_t g_ptsp;
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extern uint64_t g_ptsp_xlm;
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void bootdr(char drive) wontreturn;
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void smapsort(struct SmapEntry *);
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uint64_t *__getpagetableentry(int64_t, unsigned, struct PageTable *,
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uint64_t *);
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void flattenhighmemory(struct SmapEntry *, struct PageTable *, uint64_t *);
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void pageunmap(int64_t);
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forceinline unsigned long eflags(void) {
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unsigned long res;
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asm("pushf\n\t"
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"pop\t%0"
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: "=rm"(res));
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return res;
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}
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forceinline unsigned char inb(unsigned short port) {
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unsigned char al;
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asm volatile("inb\t%1,%0" : "=a"(al) : "dN"(port));
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return al;
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}
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forceinline void outb(unsigned short port, unsigned char byte) {
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asm volatile("outb\t%0,%1"
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: /* no inputs */
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: "a"(byte), "dN"(port));
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}
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#endif /* !(__ASSEMBLER__ + __LINKER__ + 0) */
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#endif /* APE_LIB_PC_H_ */
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